D&R Industry Articles (November 2002)

Articles for the Week of November 25, 2002

• Synthesizable Analog IP
• Easic's Zvi Or-Bach throws cold water on a semiconductor industry recovery
• BIST versus ATPG -- separating myths from reality
• The myth behind the semiconductor industry's growth-cycle guarantee
• China could make 5% of chips in 2010, says study
• Commentary: Formal platform-based design tames risks, complexity costs
• Tooling critical to project success
• COT or ASIC? No brainer for big, fast router market
• COT: post design considerations
• ASIC to COT: knowing your outsourcing options
• How Sun reduced cost /supply risk by moving to COT
• Designing a high-performance, low-cost switch fabric chip-set using COT

Articles for the Week of November 18, 2002

• FPGA to ASIC Strategy for Communication SoC Designs
• Opinion: Grappling with licensing and time to market issues
• Enforcing Design Rules to Develop Reusable IP
• SoCs need logical virtual prototype
• Pre-spec 802.11g silicon raises interoperability fears

Articles for the Week of November 11, 2002

• Foundries appear to break laws of economics
• FPGAs versus DSPs: Effective implementations of 3G basestations
• Connecting the wireless dots
• UWB simplifies portable design
• Techniques mitigate interference between 802.11 and Bluetooth

Articles for the Week of November 4, 2002

• A bluetooth radio in 0.18um CMOS
• Efficient Free-to-Air DVB-T System Solution Supported by IP-Based SoC Design
• Two platform types vie for SoC designs
• Speakers assess SoC test methods
• How to optimize programmability and speed in network processor design
• Optimized system development tools needed for programmable net processors
• Combining hard code speed with software flexibility

Articles for the Week of October 28, 2002

• Adaptive silicon comes to RF
• Commentary: Post-boom economy redefines ASICs