Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP
D&R Industry Articles (December 2002)
Articles for the Week of December 23, 2002
Additional ArticlesArticles for the Week of December 16, 2002
Additional Articles- A powerful dual-mode IP core for 802.11a/b Wireless LANs
- Flexible, standards-based IP key
- Vendors must support IP reuse in SoC
- Synthesizable IP: the risk pays off
- Nanometer scale effects complicate IP characterization
- Analog IP re-use: concerns for "digitally-oriented" SoC designers
- High-speed fabrics deliver optimal IP implementation
- Your IP: easy to protect, easy to reuse
- 7 warning signs that you should be concerned about your IP provider
- Layout compaction accelerates SoC design through hard IP reuse
- Re-use versus re-synthesize: Preparing for deep submicron issues ahead
- The five facets of SoC design complexity
- Verification reuse enables design reuse
- Closing the abstraction gap in 100M-gate designs
Articles for the Week of December 9, 2002
Additional Articles- Using Linux while avoiding costs
- Is embedded Linux the right answer?
- Telecom equipment makers must build on Linux to remain viable
- Networking driver strategies for using embedded Linux
- Why choose Linux for embedded development projects?
- Building a custom embedded SoC platform for embedded Linux
- Synthesizable Verification IP
- Mixed-signal design flow enables RF CMOS chip
- System-level issues dominate code writing
- DSP app? 80-20 rule still works
- Optimizing performance of DSPs
- Selecting DSP development tools
- Wireless SDR: overcoming next gen handset challenges
- Speeding DSP solutions with FPGAs
Articles for the Week of December 2, 2002
Additional Articles- Gate-array-like processes gain ground
- How to organize a complex SoC project
- Reduce SOC simulation and development time by designing with processors, not gates
- SEMI survey shows '02 fab-tool market to fall 32%
- Keynoter sees asynchronous future for digital designs
- Fitting DSP to app no easy task
- Wireless home multimedia networks require multiple design strategies
- Reconfigurable arrays of processors needed for wireless multimedia