D&R Industry Articles (February 2003)

Articles for the Week of February 24, 2003

• Transaction-based methodology supports HW/SW co-verification
• Application processors to drive handset IC growth
• Attacking the Verification Challenges: Applying Next Generation Verification IP to Bus Protocol-based Designs
• Hogan, Senior VP for business development at Artisan Components, sees silicon explosion as costs drop
• SystemC Verification Library speeds transaction-based verification
• Embedded wireless networking drives new ISAs for MCUs
• Multitasking operations require more hardware based RTOSes
• Commentary: HAL to push SDR out to market
• SystemVerilog key to new design paradigm
• Vendors debate viable IP business model

Articles for the Week of February 17, 2003

• Top-down SoC Design Methodology
• Assertion-Based Emulation Methodology
• External Memory Interfaces: Delivering Bandwidth to Silicon

Articles for the Week of February 10, 2003

• The case for logic BIST
• Abstract C models speed system verification
• Issues lurk behind formal equivalence checking
• SoCs are 'dead,' Intel manager declares
• SoC slam dunk still slightly out of reach
• MEMS to remain a niche technology?
• Interest in analog IP outpaces execution
• FPGA Clock Schemes
• Burning rubber on the SoC freeway
• Reaching for the 1 GHz ring
• Moving to the GHz plus range in SoC design?
• Keeping leakage current under control
• Integration by function puts more features, interfaces into handsets
• Global strategy needed for integrating IP in complex SoC design
• Adding net functions to GHz chips

Articles for the Week of February 3, 2003

• IP Modeling and Reuse for SoC Design Using Standard Bus
• Authoring assertion IP using OpenVera assertion language
• RISCy Business
• Making storage elements firmware friendly
• Avoidance proposed as solution to 90-nm problems