D&R Industry Articles (May 2003)

Articles for the Week of May 26, 2003

• Atlantic: a high-performance datapath interface for SOPC Designs
• Understanding the "e" verification language
• Semiconductor IP houses struggle to survive as ASIC design starts continue to dwindle

Articles for the Week of May 19, 2003

• Design rules push SoC packaging to the forefront
• Packaging concern: signal integrity issues rise with 500 Mbit/sec rates
• More functions require balanced SoC design
• Nanometer SoC complexities require more work in silicon, package co-design
• Systems-on-programmable chips: A look at the packaging challenges
• Co-design or bust: SoC FBGA packaging
• SoC goal staying alive: lowest cost, smallest size
• An Ethernet Security Development Platform
• The role of sockets in platform based design: a case study of the OMAP platform
• Fabless model proving less than fab
• Structured ASICs rescue endangered species
• Gbit interface forces analog IP into digital flow

Articles for the Week of May 12, 2003

• Asynchronous Logic: large CMOS devices without a clock tree
• Soft peripherals
• MPEG-4 is accelerated and footprint reduced by use of a configurable processor core
• Soft errors affect SRAM's future
• Configurable logic IP brings flexibility to SoCs

Articles for the Week of May 5, 2003

• Changes in data flow 'pipeline' needed for SoCs, new data types
• What is the impact of streaming data on SoC architectures?
• An Embedded Processor Architecture With Extensive Support For SoC Debug
• Cryptographically Enforced Pay-Per-Use Licensing of FPGA Design Intellectual Property
• Addressing System-Level Challenges in High-Speed Comm Chips
• Silicon virtual prototyping eyed for FPGAs
• Virage pulls back the covers to detail platforms
• Modules provide alternative to RF SoCs
• Semiconductor IP on a growth curve

Articles for the Week of April 28, 2003

• A system-level methodology for low power design
• USB On-The-Go presents benefits, challenges to power designers
• Design reuse is now a market necessity