D&R Industry Articles (June 2003)

Articles for the Week of June 30, 2003

• CEO Perspective: IP to shrink and stretch (By Michael Gulett, President and CEO, ARC International)

Articles for the Week of June 23, 2003

• Solving SOC Shared Memory Resource Challenges
• Techniques to make clock switching glitch free
• SoC interconnect crisis: Path delays cancel speed increase
• Metal layers a key to interconnect delay?
• Signal integrity a challenge in IC design
• COT design path eyes interconnect crunch
• Needed: High-level interconnect methodology for nanometer ICs
• Custom SoC designers must consider interconnect effects

Articles for the Week of June 16, 2003

• Finding the Right Processing Architecture for AES Encryption
• Gartner Says Semiconductor IP Companies Trying to Find the Business Model to Succeed
• Timing key to optimizing audio performance in consumer products
• In designing DDR interface, look before leaping
• Next-gen DSL: SoC doubles the data rates
• IP cores crowd SoCs

Articles for the Week of June 9, 2003

• Maximize CPU power for physical verification
• Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN
• Ten lies about microprocessors
• Test may decide choice of SoC or system-in-package
• Sometimes, the SoC integration hurdle is I/O

Articles for the Week of June 2, 2003

• Asynchronous design gets a second look
• Clockless IC designs are ready to compete
• Does asynchronous logic design really have a future?
• Clock domain modeling is essential in high density SoC design
• IP promise still can be kept
• Panel sorts out reality of 130 nm design
• TI ASIC head sees changed market
• DAC panel finds IP quality lacking
• ARM's Saxby promotes open specs, teamwork in sub-100 nm drive
• Outsourcing here to stay: DAC panel
• Silicon IP is 'immature,' execs say