D&R Industry Articles (November 2003)

Articles for the Week of November 24, 2003

• Security coprocessor ties to PCI Express
• Enter the Inner Sanctum of RapidIO: Part 1
• Enter the Inner Sanctum of RapidIO: Part 2
• ASICs becoming SoCs
• API will bridge HW/SW design gap
• Placement approach cuts SoC power needs
• Front-end analysis accelerates ASIC flow
• FPGA algorithm tunes gray, color images
• Satellite modems structure Internet access
• FPGA configures DSP core in imaging app
• FPGA is platform for ASIC-based aero system

Articles for the Week of November 17, 2003

• IP Cores for accelerating JPEG2000
• "Chip Level IP" for low power single chip wireless transceivers
• W-CDMA RAKE Receiver Comes to Life in DSP
• Collaborating to deliver open licensing for IBM PowerPC cores
• Three-dimensional SoCs perform for future

Articles for the Week of November 10, 2003

• Single-platform convergence is on track
• Keys to reconfigurable SDR system design
• Reusable architecture is DSP framework
• Comparing Current and Emerging CDMA Forward Link PHYs
• Peering into RapidIO's Move to the Data Plane
• Optical chip-to-chip connections advance

Articles for the Week of November 3, 2003

• High-speed transceivers require systems modeling
• PCI Express and Advanced Switching: different chores
• Ethernet, PCI Express ride interconnects
• RapidIO fabric is validated at system level