English
D&R Industry Articles (March 2004)
Articles for the Week of March 29, 2004
Additional Articles- Tutorial on Designing Delta-Sigma Modulators: Part 2
- Tutorial on Designing Delta-Sigma Modulators: Part 1
- The role of Verification IP in Complex core Design
- SoCs face challenges on integration road
Articles for the Week of March 22, 2004
Additional Articles- A look inside electronic system level (ESL) design
- SBATM: On-chip STBus traffic analyzer
- Embedded Virtualization Changes Comm Software Development Landscape
Articles for the Week of March 15, 2004
Additional Articles- Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning
- Variable-integration-time image sensor for wide dynamic range
- Speedy A/Ds demand stable clocks
- CMOS RF SoC design shoots for 60 GHz
- Comms rides power lines via optical AFE
- Sonet CMOS transceiver hits 10 Gbits/s
- ECC Holds Key to Next-Gen Cryptography
- Evaluating Wideband 802.11 WLAN Radio Performance
- Tackling multiple clocks in SoCs
- System-circuit view of mixed-signal design
- Hearing-aid SoC: Tiny gear, big challenges
- FPGAs step up to SoC challenge
- The Hard Truth about System-on-Chip Designs
- It Takes tools to Raise a Programmable Mixed Signal SOC
- Effective System Verification with a Scalable Verification Methodology
- Mixed-Signal Verification Methodology Using Nanosim Integration with VCS
- For SoC, It's the Whole - Not the Parts
- Solutions for Managing Complex SoC Design
- Market Focus: Chip Design Alternatives
- Standards-Based IP Cores Ease Networking IC Design
Articles for the Week of March 8, 2004
Additional Articles- Firmware friendly chip-level design techniques
- Increased Verification Productivity through extensive Reuse
- From Behavioral to RTL Design Flow in SystemC
- Mixed Signal SoC Applications
- 'A la Carte' SoCs require innovative IO management
Articles for the Week of March 1, 2004
Additional Articles- A Framework for Selection of Cache Configurations for Low Power
- Verification Methods Applied to the ST Microelectronics GreenSIDE Project
- FPGA programming step by step
- Build Complex ASICs Without ASIC Design Expertise, Expensive Tools - Take advantage of an architecture comparable to your original FPGA prototype design by migrating to a structured ASIC
- Panel ponders verification of IP
- Commentary: Less costly HW-assisted verification needed
- 90-nm FPGAs handle 10-Gbit traffic management tasks
- SoC integration changes face of high-speed line cards