D&R Industry Articles (June 2005)

Articles for the Week of June 27, 2005

• Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture
• Structured Analog ASICs using the Mentor Graphics tool flow
• How to improve verification planning
• How to navigate analog/digital gulf

Articles for the Week of June 20, 2005

• Adapting partially programmable ASSPs to vehicle design needs
• Accelerating Nios II Ethernet Applications
• Application Specific Real-Time Microkernel in Hardware
• IP Processor Core Platform Selection According to SoC Architecture: a case study
• Managing multiple evaluations of analog IP
• Equivalency checking verifies sequential changes
• Revving video encoding on C64x/DM64x DSPs

Articles for the Week of June 13, 2005

• Embedding FPGAs in DSP-driven Software Defined Radio applications

Articles for the Week of June 6, 2005

• Transaction-Level Modelling and Debug of SoCs
• Fit multimedia handsets with the right memory architecture
• Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm
• Optimize performance and power consumption with DSP hardware, software
• Top-down approach speeds mixed-signal design
• Electronic system-level development: Finding the right mix of solutions for the right mix of engineers

Articles for the Week of May 30, 2005

• Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects
• The Challenge of Keeping IP Usable