D&R Industry Articles (December 2005)

Articles for the Week of December 26, 2005

• A practical approach to reusing HDL code in FPGA designs
• An introduction to symbolic simulation

Articles for the Week of December 19, 2005

• Delivering the benefits of C++ encapsulation to your embedded design
• Mapping custom instructions for the Toshiba media embedded processor (MeP)
• How to make your asymmetric multiprocessor design OS and CPU independent
• A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip

Articles for the Week of December 12, 2005

• Successful Use of an Open Source Processor in a Commercial ASIC
• How to use register retiming to optimize your FPGA designs
• How to adapt traditional RTOSes to symmetric multiprocessing
• Large Memory Modeling
• Automated tool suite speeds SoC design

Articles for the Week of December 5, 2005

• OCP-based memory access arbitration for a digital sampling oscilloscope
• Network require multi-gigabit processing? Try multi-core FPGAs
• Using SystemVerilog for functional verification