D&R Industry Articles (February 2006)

Articles for the Week of February 27, 2006

• Simulating and debugging multicore behavior
• FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
• The 'what' and 'why' of transaction level modeling

Articles for the Week of February 20, 2006

• Securing ad hoc embedded wireless networks with public-key cryptography
• Risk versus Reward: Where Do Your IP Reuse Practices Fall?
• The state-of-play in multi-processor and reconfigurable computing
• How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications
• A Unified DFT Verification Methodology
• OTP firmware enhances processor flexibility

Articles for the Week of February 13, 2006

• How much test compression is enough?
• High Speed Connected Component Labeling as a Killer Application for Image Recognition Systems by Dynamically Reconfigurable Processor
• Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP
• Business Considerations in SoC IP Procurement
• Reengineering the obsolete semiconductor

Articles for the Week of February 6, 2006

• Real-Time Video System Design Based on the NIOS II Processor and µCLinux
• CE-ATA: Consumer Electronics Storage Technology Introduction and Hardware Design Challenges
• Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Reference Verification Methodology (RVM)
• Unique Approach to Verification of Complex SoC Designs
• Understand the fundamentals of speech algorithms in an embedded system
• Compiling FPGA netlists for formal verification

Articles for the Week of January 30, 2006

• Debug IP for SoC Debug
• Choosing hardware IP
• FPGAs add flexibility to communications traffic management