D&R Industry Articles (May 2006)

Articles for the Week of May 29, 2006

• How to reduce simultaneous switching output noise with a stand-alone SerDes
• A bridging model for ESL synthesis
• A Novel Modeling and Verification Environment for Rapid IP Prototyping
• Cortex-R4 -- A comparison with the ARM9E processor family

Articles for the Week of May 22, 2006

• Favorable Economics Will Drive Rapid Adoption of Certified Wireless USB
• A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach
• A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs
• ARM Cortex-R4, A mid-range processor for deeply-embedded applications
• How assertions can be used for design

Articles for the Week of May 15, 2006

• Inside CEVA's portable, programmable video solution
• Connecting reality and simulation: Couple high speed FPGAs with your HDL simulation
• Low Power Design Methodology for Core based ASSP
• Rethinking System-on-chip design at 65 nanometers and below
• Sequential equivalence checking supports ESL flow
• Hardware/Software Partitioning and Interface Synthesis in Networks On Chip

Articles for the Week of May 8, 2006

• Use compression where it's never gone before: A/D and D/A converters
• Reverse Disaggregation - How Silicon IP Will Change the Semiconductor Supply Chain
• Embedded NVM adds flexibility to power management designs
• How hybrid Structured ASICs provide low cost solutions for mid-range applications
• A NoC-based Communication Framework For Seamless IP Integration in Complex Systems
• OCP 'tags' support high-performance SoCs

Articles for the Week of May 1, 2006

• Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
• A low-cost solution for FPGA-based PCI Express implementation
• Verification Methodology for Standards-based IP & SOC
• Automated Implementation Flows based on IP-level constraints and synthesis intent in XML
• SystemVerilog reference verification methodology: RTL