D&R Industry Articles (June 2006)

Articles for the Week of June 26, 2006

• Embedded Linux Co-simulation
• How to speed FPGA debug with measurement cores and a mixed-signal oscilloscope
• Scale network processors to 40 Gbps and beyond
• Legacy RTL brought into system-level flow
• Constraint-driven physical design speeds IC convergence
• Design and FPGA Implementation of an Interpolative Neural Network for Digital Image Zooming

Articles for the Week of June 19, 2006

• How to implement an open IP encryption flow
• 5c Over AV Link: A Comparison of Architectures
• Core-assisted approach accelerates debug of FPGA DDR II interfaces
• Cycle Accuracy Analysis and Performance Measurements of a SystemC model
• Sequential equivalence checking for RTL models
• Design and verification strategies for complex systems: Part 2

Articles for the Week of June 12, 2006

• Picking the right 802.15.4/ZigBee wireless connection for your embedded design
• A Case Study in Rule-Based Modeling
• Design and verification strategies for complex systems, part 1
• High Quality IP creation through Efficient Packaging and Multiple Configuration Testing
• SystemVerilog reference verification methodology: ESL
• System-on-chip bulk CMOS can cause a paradigm shift

Articles for the Week of June 5, 2006

• FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM
• Implementing PCI Express Designs using FPGAs
• The need for verification management
• Broadcast video infrastructure implementation using FPGAs
• Facilitating System-in-Package (SiP) design
• Efficient creation of peripheral simulation from specifications

Articles for the Week of May 29, 2006

• Automated video algorithm implementation
• The Perils of RF IP