D&R Industry Articles (November 2006)
Articles for the Week of November 27, 2006
System on Chip (SoC) for Short Range Wireless - CMOS versus SIGe
Wireless communication is becoming more and more commoditized. While newer technologies such as UWB and 802.11n are still in the early adopter phase, with time to market being the primary driver, the markets for Bluetooth and 802.11abg are maturing, meaning that cost reduction becomes the primary goal- Focus on FPGA programmable platform for industrial systems
- Tutorial: Programming High-Performance DSPs, Part 1
- Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
Articles for the Week of November 20, 2006
Media SoC design for reduced power consumption
Architectures that are ''power conscious'' use design techniques to reduce the overall gate count and power consumption while efficiently handling data transactions.- We Need ''Enterprise'' System-Level Solutions
- Achieving multicore performance in a single core SoC using a multi-threaded virtual multiprocessor: Part 1
- Using high integration SoC alternatives for your legacy X86 design
- DSP optimization strategies using simulators and profilers
Articles for the Week of November 13, 2006
Optimizing the Implementation of Dolby Digital Plus in SoC Designs
This white paper outlines the benefits of Dolby Digital Plus for select key consumer audio markets and details the processes behind the collaborative effort between MIPS Technologies and Dolby Laboratories.- Tutorial: Improving the transient immunity of your microcontroller-based embedded design - Part 2
- Integrating 'hard' IP into a system-on-chip
- Speed up downconverter implementation with rapid prototyping
- Integrating an H.264 video encoder with Stretch's processor
Articles for the Week of November 6, 2006
Diamond Standard Processor Core Family Architecture
This white paper explores the design of the Xtensa base instruction set architecture (ISA) and illustrates the impact of architecture on performance. It traces the evolution of modern instruction-set design and compares key features of Tensilica’s architecture with previous instruction set architectures. It provides a detailed rationale for the major architectural innovations in the Xtensa ISA.- Tap into the advantages of a scalable OFDMA engine for WiMAX
- Embedded multicore needs communications standards
- How to get more performance in 65 nm FPGA designs
- Tech Tutorial: Message buffers provide FlexRay versatility
- Special Preview: BDTI's FPGAs for DSP, Second Edition
Articles for the Week of October 30, 2006
Future Trends in SoC Interconnect
Self-timed packet-switched networks are poised to take a major role in addressing the complex system design and timing closure problems of future complex Systems-on-Chip.