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D&R Industry Articles (January 2007)
Articles for the Week of January 29, 2007
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A Security Tagging Scheme for ASIC Designs and Intellectual Property Cores
This paper introduces a novel idea for labelling and protecting electronic designs and in particular Intellectual Property (IP) Cores, implemented in Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs).- How to architect, design, implement, and verify low-power digital integrated circuits
- Five steps to FlexRay
Articles for the Week of January 22, 2007
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An Analog Verification and IP Development Environment
This paper describes the prototype of an environment for block and sub-system analog design supported by cell-reuse and circuit-class specific templates. It brings software tools and design knowledge together which leads to higher design effectivity and quality by smoothly enhancing the usual design style.- Design Security in Stratix III Devices
- How to design 65nm FPGA DDR2 memory interfaces for signal integrity
- Using PCIe in a variety of multiprocessor system configurations
Articles for the Week of January 15, 2007
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USB 2.0 PHY Verification
In this paper we present a Vera-based reusable environment to verify a USB 2.0 PHY that addresses some of the problems of a typical PHY Verification. Thus, we present the developed VIPs such as monitors, response checkers and functional coverage object needed to be re-used for multiple PHY implementations, as well as potentially in an integrated Controller/PHY testbench.- How to Choose the Right FPGA
- Utilizing OCP to design a high performance interconnect
- Defining the TLM-to-RTL Design Flow
- How to achieve faster compile times in high-density FPGAs
- Planning for assertion-based verification
- How to maximize FPGA performance
- Video and image processing design using FPGAs
Articles for the Week of January 8, 2007
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DDR Memory Systems at the Heart of Consumer Electronics
In this article, DDR memory systems will be discussed in the context of consumer electronics design, with an emphasis on the need for a multi-disciplined, system-level approach. A brief look of relevant market pressures are followed by review of key issues in memory system development, including device selection, controller and PHY (Physical) design, and system integration. The article concludes with an example of commercially available solutions that address the key issues.- Hard IP Core Placement Method in VLSI Physical Design
- Main profile H.264 codec: A low power implementation for consumer applications
- FPGAs vs. DSPs: A look at the unanswered questions
- Top 10 methods for ASIC power minimization -- Part 2
- Top 10 methods for ASIC power minimization -- Part 1
- DVB-H handheld video content protection with ISMA Encryption
- C based design methodology accelerates ASIC/FPGA design cycles
Articles for the Week of January 1, 2007
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Design and Real Time Hardware Implementation of a Generic Fuzzy Logic Controller for a Transport/Diffusion System
A fuzzy controller design methodology for the control action in the transport/diffusion is presented here. The efficient design of the controller according to the desired specifications using VHDL and its implementation on FPGA introduces a novel approach for realizing a generic prototype of the controller, applicable in real time systems.