D&R Industry Articles (August 2007)
Articles for the Week of August 27, 2007
Distributed Software Behaviour Analysis Through the MPSoC Design Flow
The complexity of developing Systems-on-Chip (Soc) is increasing continuously, but the productivity of hardware and software developers is not growing at a comparable pace. As a consequence, the conception of a new SoC can take a few years and software can’t wait its availability.- Using an open debug interconnect model to simplify embedded systems design
- Ultra-low-power DSP design
- Analysis: ARC's Configurable Video Subsystems
- Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification
- SoC technology underscores need for verification
Articles for the Week of August 20, 2007
Smart InterConnects with Smart IP: Joint Enablers for Rapid MultiMedia SoC Development
For the past decade, the march of Moore’s “Law” has witnessed the phenomenal growth in System on Chip (SoC) gate counts, allowing the implementation of a confluence of sophisticated algorithms at price points feasible for consumer electronics (e.g., HDTVs, DVD recorders, multi-functional mobile phones, etc.). Unfortunately, gate counts over the past decade have grown far faster than IC designers’ productivity. With so much pressure to launch high end consumer products before prices (and margins) erode, generations change, new standard features are added, and additional competition surfaces, every aspect of the design flow requires analysis to see how, if, when, and where time-to-silicon can be shortened.- Locking Down Intellectual Property in Embedded Systems
- How to support multiple SD devices using CPLDs
- Implementing an FPGA-based scalable OFDMA engine for WiMAX
- DSP silicon takes many forms
Articles for the Week of August 13, 2007
IP Core for RAID 6 Hardware Acceleration
As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.- Practical design considerations -- Ethernet vs. RapidIO standards
- Verification methodologies keep pace with complex IP
- Accelerate system performance with hybrid multiprocessing and FPGAs
Articles for the Week of August 6, 2007
Systel Level Design Automation of Pipelined ADC
In this paper a design automation technique for pipelined analog ¨C to ¨C digital converter (ADC) is presented, the aim is to automate the design of a switched capacitor pipelined analog ¨C to ¨C digital converters and to extract the circuit level specifications (spec¡¯s) from system level by modeling the most important circuit non-idealities effects on effective number of bits (ENOB).- Embedded developers should embrace FPGAs
- Overcoming Wireless USB commercialization challenges
- Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor
- Designing with proven implementations of the Inter IC bus
- Making Verification Methodology and Tool Decisions
- Embedded test offers unique value for serial I/O
- How video compression works
Articles for the Week of July 30, 2007
Additional Articles- Analysis: Tensilica's D1 Video Engine
- Facilitating technology insertion in advanced wireless systems