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D&R Industry Articles (December 2007)
Articles for the Week of December 17, 2007
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Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format
In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.- Efficient testbench implementation for verification proposed by Synopsys staffer
- Do the Math: Reduce Cost and Get the Right Communications System I/O Connectivity
- The role of secure memory in a trusted execution environment
- Lower the cost of intelligent power control with FPGAs
- Achieving Yield in the Nanometer Age
- KNOW THE ISSUES: Applying FPGAs in system-critical automotive electronics
- Using Off-the-Shelf Technology with an FPGA to Replace Custom Hardware
Articles for the Week of December 10, 2007
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Staged Scenario Generation For SoC Verification
This paper presents a staged scenario generation methodology for SoC verification to control, reuse and scale transaction generation from device level verification to system level verification. This methodology can provide various levels of transaction generation abstraction to reuse, control and scale stimulus to generate test scenarios for device level as well as system level.- Designing DDR3 SDRAM controllers with today's FPGAs
- Combining C code with assembly code in DSP applications
- Applying Constrained-Random Verification to Microprocessors
- Partitioning applications across multiple cores
- Virtually every ASIC ends up an FPGA
Articles for the Week of December 3, 2007
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Case study of a complex video system-on-chip
The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) systems-on-chip (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges. A collaborative effort among IC designers using CoWare's ESL tools and Sonics' SMX smart-interconnect IP designed for this class of SoCs enabled the rapid optimization and verification of the design aspects necessary to meet the critical architectural challenges.- A revolution in functional verification
- Leveraging system models for RTL functional verification
- Efficient radix-4 FFT on StarCore SC3000 DSPs