D&R Industry Articles (June 2008)

Articles for the Week of June 30, 2008

Featured Article

Generic Driver Model using hardware abstraction and standard APIs

This paper describes a unique approach for developing drivers using hardware abstraction and standard APIs for hardware and software interfaces.

• Low power design for analog/mixed signal IP
• Use NAND Flash for cost, density and performance advantages for mobile handsets

Articles for the Week of June 23, 2008

Featured Article

Straightforward IP Integration with IP-XACT RTL-TLM Switching

This paper gives the results of experimentations done for the packaging of a USB OTG controller respecting the IP-XACT schema provided by The SPIRIT Consortium

• Leveraging Virtual Platforms for Embedded Software Validation: Part 2
• How to select CPLDs for handheld applications
• SoCs can hold key to system security
• Integration of Design-for-Analysis in IC Layout Considerations to meet the Challenges of Shrinking Technology
• Single Flow for Interconnecting IP
• Lower voltage next goal for low-power DDR

Articles for the Week of June 16, 2008

Featured Article

Advanced Techniques for IP Design and Verification

SystemVerilog for design, power aware design and verification flow, dynamic and formal property verification and transaction level debugging for viewing signals at a higher abstraction level are some of the new techniques getting more attention in the design and verification space.

• Keeping the best audio quality in mobile phone by managing voltage drops created by 217 Hz transients
• ESD and EMI hazards in mobile phones--Solutions for the audio system connector
• Leveraging virtual hardware platforms for embedded software validation

Articles for the Week of June 9, 2008

Featured Article

Mixed-Signal Verification for USB 2.0 Physical Layer IP

A well planned verification flow for a mixed-signal IP is required to achieve the highest quality of the IP performance with the expected design specifications. The aim of this paper is to present a mixed-signal verification flow for the Universal Serial Bus physical layer IP.

• eTBc: A Semi-Automatic Testbench Generation Tool
• Mobile DDR spurs low-cost, low-power automotive electronics designs
• Bridging the Gap Between Silicon and Software Validation
• Analysis: Altera jumps to 40 nm with Stratix IV

Articles for the Week of June 2, 2008

Featured Article

Adapter Based Distributed Simulation of Multiprocessor SoCs Using SystemC

An ever increasing demand for execution speed and communication bandwidth has made the multi-processor SoCs a common design trend in today’s computation and communication architectures.

• Floating-point emulation: faster than hardware?
• Enhance circuit timing design with programmable clock generators (Part 1 of 2)
• Enhance circuit timing design with programmable clock generators (Part 2 of 2)
• Leveraging Design Insight for Intelligent Verification Methodologies
• Xilinx responds to Altera's FPGA benchmarks