D&R Industry Articles (January 2009)
Articles for the Week of January 26, 2009
Identifying IP cores -- to protect your investment
In this paper, Semiconductor Insights shows some noble ways of identifying IP cores from any SoC products to protect the interest of IP core providers. Techniques developed by Semiconductor Insights to identify IP core blocks include methods such as circuit extraction using advanced delayering techniques, layout comparisons, automatic recognition and extraction of standard cells and blocks of designs, netlist generation from the extracted circuits, use of circuit library to identify IP blocks, use of structural data mining algorithm for netlist comparison, and device and system level testing to identify IPs involving algorithms and system level protocols.- Programmable logic innovation is overdue
- How SLEC improves functional verification
- SAS--SATA: What You Need to Know for 6 Gb/s and Beyond
- MCU debug on a pin-count budget
Articles for the Week of January 19, 2009
The Value of High Quality IP-XACT XML
As the semiconductor industry increases take-up of IP-XACT standards to describe Intellectual Property (IP) this paper shares the experiences of NXP Semiconductors and Mentor Graphics, who have been using and developing this technology together for over five years. This paper describes the benefits of adopting IP-XACT and highlights the importance of producing high quality component XML as the foundation of a successful IP-XACT reuse strategy.- Viewpoint: Competitive Advantage vs. Collaborative Advantage
- Implementing a processor-independent, battery-powered wireless mesh network
- The promises--and pitfalls--of open mobile platforms
- Tips and Tricks: Using FPGAs in reliable automotive system design
- Filter banks, part 1: Principles and design techniques
Articles for the Week of January 12, 2009
Inductorless versus Inductor-Based Integrated Switching Regulators: Bill Of Material, Efficiency, Noise, and Reliability Comparisons
Inductor-based Switching Regulators (SR) have historically represented the preferred architecture for power supplies. Nowadays, for low-power and highly integrated electronic systems, embedded inductor-based SRs show several limitations that can be overcome by the use of inductorless SR architectures. This paper provides a qualitative and quantitative comparison between both types of SR in terms of implementation cost (Bill of Material, and pin count), and performance (efficiency, noise, and reliability).- An application modeling & hardware description for network-on-chip benchmarking
- Backplane tutorial: RapidIO, PCIe and Ethernet
- How to transform video SerDes from a nightmare to a dream
- Doing ESL system validation using transactors
- Architecting the OCP uVC verification component
- PRODUCT HOW-TO: Taking the delay out of your multicore design's intra-chip interconnections
- Using yesterday's methodologies to design today's multi-FPGA systems is a recipe for disaster
Articles for the Week of January 5, 2009
Additional Articles- Providing memory system and compiler support for MPSoc designs: Memory Architectures (Part 1)
- Providing memory system and compiler support for MPSoc designs: Customization of memory architectures (Part 2)
- Providing memory system and compiler support for MPSoc designs: Compiler Support (Part 3)
- Innovating methodology beyond base classes
- Differentiate your HD multimedia design by customizing the processor core
- Turbo encoders boost efficiency of a femtocell's DSP