D&R Industry Articles (March 2009)

Featured Article

Learning Not to Fear PCI Express Compliance Using a Predictable, Metrics Based Verification Closure Methodology

On the way to taping out its first PCI Express based SOC, ClearSpeed came face-to-face with the many difficulties of ensuring PCI Express protocol compliance within time and budget constraints. PCI Express is a complex protocol with an extremely large coverage space. From a management perspective, there is simply not an alternative but to apply a metrics-driven verification process to ensure protocol compliance.

Featured Article

Developing Assertion IP for Formal Verification

Assertion language provides a way to express the properties and constraints for property based formal verification environment. Current assertion languages such as SVA and PSL offer a great set of constructs that enables one to write assertions in number of ways. his paper covers certain coding guidelines which should be considered while developing a formal friendly assertion based IP.

Featured Article

Pipeline vs. Sigma Delta ADC for Communications Applications

The Analog-to-Digital Converter (ADC) is a key component in digital communications receive channels, and the correct choice of ADC is critical for optimizing system design. In this article, we discuss what design factors drive the selection of the ADC, how to specify the ADC and when to choose between a Pipeline ADC and a Sigma-Delta (Σ/Δ) ADC.

Featured Article

Debug and testability features for multi-protocol 10G Serdes

The paper describes the design-for-test (DFT) features of a 10.3125Gb/s Serdes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations.

Featured Article

Analog IP Integration in SoC: Challenges and Solutions

This paper introduces detailed methodology guidelines for successful analog IP integration in SoC. The guidelines described in this paper are based on thorough root cause analysis of real design issues related to analog IP from several SoC designs. The knowhow of issues prior to design tapeout and ensuring compliance to guidelines listed in this paper had been successful in significantly reducing design re-spins and getting closer to fully functional first time right device.