D&R Industry Articles (April 2009)

Featured Article

Advances in SoC and Processor Modeling Methodologies

Increasing complexities of the programmable components demand newer modeling methodologies. Architects need to evaluate various design constraints in a short time and also generate tools for the new architecture. Although SoC and processor modeling has been around for a long time, newer methodologies are still being put forward to overcome limitations like limited architecture modeling capabilities, slower simulation speeds, little/less validation support, issues with synthesis, etc.

Featured Article

Practical Design and Implementation of a Configurable DDR2 PHY

To reduce the hassles presented to SoC designers by the DDR2 interface, many problems have been resolved by DDR2 PHY IP development. A DDR2 high speed PHY block is almost always developed as a full custom mixed signal design. There are many good reasons for implementing a full custom design, where every cell and every signal route is fully controlled. Such pre-defined, hard designs offer a way to deal with the tight timing budget of DDR2, which is in the range of a few tens of picoseconds. Another reason is the physical dimensions in which this block must fit. This paper presents through examples of the methods selected while performing physical implementation of the IP.

Featured Article

SOC Virtual Prototyping: An Approach towards fast System-On-Chip Solution

In this paper, we discuss the Transaction Level Model which is being developed to act as Virtual Prototype in digital image processors designed to fit into mobile applications. As part of our developments new methodology TLMdevice is also defined which provides way to connect TLM simulations to communicate with not only virtual host devices such as Graphical window, Keyboards but also real host devices like UART, Display and Sensors, so that data can be easily sent and received to/from during TLM simulation run

Featured Article

SoC IP Interfaces and Infrastructure -- A Hybrid Approach

This paper presents three generations of SoC designs beginning with a flat single AHB Bus based interconnect, followed by a multi-tier AHB/APB segmented communication infrastructure and finally our hybrid approach using both the AHB bus for control path operations and point to point BVCI connections through an internal crossbar for data flow. This architecture eliminates many of the dataflow bottlenecks common to SoCs and leaves the device constrained only by processing power and DRAM bandwidth. The power benefits of the architecture are also discussed throughout.