D&R Industry Articles (May 2009)

Featured Article

A Re-Usable Level 2 Cache Architecture

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced support for data prefetch, coherency, and performance monitoring. Results are presented showing the performance improvement profile over a large class of applications.

Featured Article

New Applications Areas Driving Higher Dynamic Range Converters

With the advent of higher broadband speeds in the fixed line and wireless systems, the need for higher performing data converters has become apparent. In this article, we discuss the different standards that are pushing this trend and how single tone testing, in some cases, does not accurately determine the performance in communication systems.

Featured Article

Security Challenges in Embedded Designs

We present several use-cases where embedded security is a fundamental requirement. For each use-case, we list a set of security-related characteristics and translate these characteristics into security requirements. We continue by analyzing the security requirements and identifying the embedded security building blocks of each one.

Featured Article

A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoC

In this paper, we present a methodology for performance analysis of the interconnection network, with focus on video and multimedia benchmarking. We describe a typical video decoder based SoC system, and describe the traffic profiles for each of the processing engines. We also provide performance analysis measures of interest in a video decoder based SoC.