D&R Industry Articles (October 2009)

Featured Article

Adding Hardware Acceleration to the HVL Testbench

This paper describes a framework where advance HVL based testbench can be reused to generate the hardware acceleration platform to overcome simulation speed bottleneck and save bring up time of such effort. The various schemes to maximize the performance of hardware acceleration solution are also mentioned in the paper.

Featured Article

Memory Power Reduction in SoC Designs Using PowerPro MG

SoCs that integrate multiple functions on a single silicon die are at the heart many electronic devices enabling designers of such systems to meet their specifications in terms of functionality, performance, cost and power. As process geometries have scaled, design teams have used more and more of the additional silicon real estate available on chips to integrate embedded memories that serve as scratch-pads, FIFOs and caches to store data for the computational cores. These embedded memories allow for significantly better system performance and lower power compared to a solution where off-chip memories are used.

Featured Article

Customizable SoC SPEAr from STMicroelectronics Solving Time to Market Issues

Some of the most common known issues any equipment manufacturer needs to solve are Time To Market and Time To Volume strong constraints. These issues are also linked with an increased fragmentation of the final products portfolio to be offered, even if often these products are using the same kernel of basic SoC product. SPEAr concept is one of the most suitable versatile but standard SoC for a customer to solve these issues