D&R Industry Articles (November 2009)
Articles for the Week of November 30, 2009
Additional Articles- Accelerating Bioinformatics Searching and Dot Plotting Using a Scalable FPGA Cluster
- PRODUCT HOW-TO: Increase embedded processor efficiency through the use of distributed processing blocks
- Using IEEE-1588 transparent clocks to improve system time synchronization accuracy
Articles for the Week of November 23, 2009
Additional ArticlesArticles for the Week of November 16, 2009
EDA tools and Design Methodology for multi-FPGA Designing/ Prototyping
As the cost of mask is increasing and the performance gap between FPGA and ASIC is reducing the FPGA is evolving a strong platform for not-only prototyping but also as a platform for real time design. But one of the major challenges that still remains is using of FPGA for large SoC design.- High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems
- SaaS and EDA: Are designers ready?
- Multisite, collaborative hardware design calls for HCM
- Use formal, online communication to deliver design quality closure
Articles for the Week of November 9, 2009
Incorporating Quality into Reusable Interface IP
Today’s complex silicon-on-chip (SoC) designs contain multiple instances of silicon intellectual property including CPUs, DSPs, and large numbers of interface IP—SD, SDIO, USB, and MIPI—to store and route video, audio, and data within these designs. On some large SoCs, as much as 85 percent of silicon real estate is made up of third party IP.- Using OCP and Coherence Extensions to Support System-Level Cache Coherence
- Boundary scan and JTAG emulation combine for advanced structural test and diagnostics
- Multi-core, multi-IP reduce development time for infotainment apps
- The best of both worlds: Optimizing OCP slave memory behavior
Articles for the Week of November 2, 2009
Femtocells Gather Momentum - Security Design is Pivotal to Consumer Acceptance
AT&T customers in Charlotte, North Carolina have the good fortune of being the latest subscribers that are can now able to sign-up for a femtocell which offers consumers reliable, high-bandwidth mobile services at home. A femtocell is a miniaturized version of a cell site that a customer installs at home and connects to a DSL or cable modem. This article offers background on how femtocell networks are constructed, offers a snapshot on standardization and interoperability efforts and then digs in to the important security requirements that are vital to successful deployment of femtocells.- Enable low power design with FPGAs
- Graphics processing: When DIY just doesn't make sense
- Stochastic Computation applied to the design of Error Correcting Decoders
- Migrating ARM7 Code to a Cortex-M3 MCU (Part 2)
- Migrating ARM7 code to a Cortex-M3 MCU
- An UML-driven Interface Generation Approach for SoC Design