D&R Industry Articles (August 2010)
Articles for the Week of August 30, 2010
Additional ArticlesArticles for the Week of August 23, 2010
Reusable Device Simulation Models for Embedded System Virtual Platforms
This paper discusses the class of virtual platforms called host simulations. With host simulation, the embedded application code is compiled for the host processor using native compilers and executed directly on the host machine. This paper presents the characteristics of reusable device simulation models, and the methods to design and implement them. It also discusses the steps required to execute an embedded application code on a host machine using host simulation.- How audio processing algorithms help improve sound from small speakers
- Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet
- Commentary: How strong are your IP assets?
- Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs
- Dual core architectures in automotive SoCs
- System Verilog configurable coverage model in an OVM setup - concept of reusability
Articles for the Week of August 16, 2010
Additional Articles- How throughput enhancements dramatically boost 802.11n MAC efficiency--Part II
- Using switched capacitors to create programmable analog logic blocks in mixed-signal designs
- Reusability, usability and flexibility
- How to use FireWire for innovative new designs without distance constraints
- A case for not choosing the latest components
Articles for the Week of August 9, 2010
Additional Articles- Comparing AMBA AHB to AXI Bus using System Modeling
- How throughput enhancements dramatically boost 802.11n MAC efficiency--Part I
- Reduce embedded SoC design cost & optimize IP integration
- FPGA compilation on-site or in the cloud
Articles for the Week of August 2, 2010
Using in-design physical verification to reduce tapeout schedules
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.- Picking the right built-in self-test strategy for your embedded ASIC
- Use XML to build ASIC or SoC design specifications