D&R Industry Articles (October 2010)

Featured Article

Application Specific IP - Ensuring Semiconductor IP Quality

One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP’s quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the Die contains the IP block separated from the System-on-a-Chip (SoC) . It is, though, uncertain how the block will function in ASSP and ASIC products, potentially damaging its perceived commercial value.

Featured Article

SATA Connectivity solutions for Xilinx FPGAs

This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE).

Featured Article

HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures

In this paper, we present a code generation flow to deploy system applications over hardware architectures based on abstract descriptions. Our approach is defined in two steps: a front-end step which deals with abstract description of the application, the architecture (in extended IP-XACT), the mapping, and a back-end step which incorporates specific platform details necessary for HW/SW interface generation. A case study on the deployment of a complex 4G telecommunication application on a heterogeneous multi-core platform is also presented.

Featured Article

How to Choose Great IP

Many chip designers use IP to improve their productivity, but unfortunately not all IP is created equal. Ed Bard, senior director of marketing, IP, and Ralph Morgan, vice president of engineering, IP, both of Synopsys, suggest that to separate the good from the bad, design teams must exercise proper due diligence when selecting IP.