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D&R Industry Articles (January 2011)
Articles for the Week of January 31, 2011
Featured Article
Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology
As System-on-chip (SOC) developers continue to look for ways to reduce cost and time to market, it is important to consider the different non-volatile memory (NVM) options that add flexibility to their products. Over the last few years, the NVM market has been flooded with new solutions. Now, having customers weigh the benefits of reliability, options, and costs during project development is even more critical. With antifuse vendors targeting a wider range of functionality and products, noting the reliability concerns of reaching hard breakdown (HBD) compared to soft breakdown (SBD) is vital.Articles for the Week of January 24, 2011
Additional Articles- 7 myths of analog and mixed-signal ASIC design
- How to instrument your design with simple SystemVerilog assertions
- Free I/O: Improving FPGA clock distribution control
Articles for the Week of January 17, 2011
Additional Articles- Multiband architecture for high-speed SerDes
- How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
- Managing coverage grading in complex multicore microprocessor environments
- Using co-design to optimize system interconnect paths
- Designing an FPGA-based graphics controller
- Mixed-Signal Designs: The benefits of digital control of analog signal chains
Articles for the Week of January 10, 2011
Featured Article
Additional Articles
Is there a "one-size fits all" SOC PLL?
Like most types of circuits, there is no such thing as a "one size fits all" PLL. This article will explore the trade-offs in PLL performance and design and look for a solution to most SOC PLL needs.- Scalable architectures for high-bandwidth Ethernet line cards
- An RTL to GDSII approach for low power design: A design for power methodology
Articles for the Week of January 3, 2011
Featured Article
Additional Articles
Configurable VESA - VGA and DVI Test Pattern Generator
This paper is presented with the Video Graphics Array (VGA) and Digital Visual Interface - Digital (DVI-D) test pattern generator solution with display monitor timing specification as per the Video Electronics Standards Association (VESA) to address the VGA and DVI-D video processors RTL verification and chip validation requirements.- When perfect is good enough
- Architecting hardware, software & communications for the electronic battlefield