D&R Industry Articles (February 2011)

Featured Article

MIPI™ MPHY - An introduction

Recognizing the need for high bandwidth pipes, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane.

Featured Article

Routing Congestion: The Growing Cost of Wires in Systems-on-Chip

This paper presents trends in technology, introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.

Featured Article

Integration Optimized SuperSpeed USB3.0 IP from Cadence - Delivering Superior Value to the SOC Designer

Designs are moving towards a hierarchical structure, collection of individual subsystems each with a local interconnect CPU, DSP, and memory, and a global interconnect tying all these subsystems together, along with intelligent Interface IP, and multichannel memory. The pain points faced by the customer in today's world, is in obtaining and integrating enormous amount of IP, having to verify a system that comprise of SOC hardware and software, creation and validation of software, and not to mention the least, hitting schedule and budget.