D&R Industry Articles (March 2011)
Articles for the Week of March 28, 2011
Additional Articles- Attofarad accuracy for high-performance memory design
- Complete NAND Flash Solution: Logic, PHY and File System Software
Articles for the Week of March 21, 2011
Vertically Integrated MIPI Solutions
The emerging MIPI standards are designed to ensure interoperability among devices and software that are used in products for the exploding hand-held market. The standards facilitate the interconnection of multiple, mixed-signal integrated circuit devices on a single hand-held product. Use of the standards ensures low power, low pin count and interoperability of all the devices in the system and easy integration.- System awareness improves SOC power management
- Hardware Configuration Management and why it's different than Software Configuration Management
- The real role of EDA in the Cloud
- Using simulation and emulation together to create complex SoCs
- Analog IP for multimedia SoCs: an eye on a world of essential analog features
- What’s the number of ASIC versus FPGA design starts?
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
- What makes an optimal SoC verification strategy
Articles for the Week of March 14, 2011
A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design
In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of power gating (P.G.) MOS is especially considered for the compiler design. The proposed method achieves an obvious advantage in leakage control of low leakage mode for memory compiler. Simulation data shows a 4× leakage reduction for retention mode, and a 50× leakage reduction for sleep mode for a 512k density instance compared to original design.- Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
- Hardware/Software integration: Closing the gap
- Test tools to empower engineers for PCIe 3.0 designs
Articles for the Week of March 7, 2011
Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform
This article talks about VIP architecture requirement for achieving Hardware Accelarated Verification using on board generation, error checker, data checker and coverage collection, taking example of AHB Synthe-sizable VIP- Planning reset strategy: Flow & functionality in OVC
- How manycore will reshape EDA
- Major changes expected for physical verification tools as designs move into 28nm and below
- Using PCI Express as a fabric for interconnect clustering
- Introduction to SVA Assertions for Design Engineers
- CPUs in FPGAs: many faces to a trend
Articles for the Week of February 28, 2011
Additional Articles- STOP! Are You Gambling On Your Memory IP?
- Expediting processor verification through testbench infrastructure reuse
- Adding encryption to disk drives is made easy using an IP core
- Think static analysis cures all ills? Think again.
- CoreMark: A realistic way to benchmark CPU performance
- Mixed-Signal = Analog + Digital, or is there more to it?