D&R Industry Articles (April 2011)

Featured Article

An IP-XACT Deployment Case: IZARN IP

This document presents an IP-XACT deployment case on a complex IP, called IZARN. IZARN is a digital IP which includes an ARM CPU and is targeted to be used in a SoC (System on Chip) for mobile phones.

Featured Article

Cache Evaluation Software: A Dynamically Configurable Cache Simulator

The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a good way to reduce power consumption. However application programs are complex and include many subroutines, each of them having their own optimal cache configuration. We developed a low power dynamically reconfigurable cache controller and its simulator called Cache Evaluation Software.

Featured Article

Minimal Effort Chip Design Using IP

In order to speed up design cycles and to reduce development costs, use of external IP is increasingly becoming more popular. However, this IP based design is not free of considerable effort and saves only about half of the effort required to develop the IP internally. The concept of Intelligent Design Automation (IDA) is presented here which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, and multi-criteria optimization. This paper also presents the idea of IP Integration Automation,or I2A, tools.

Featured Article

The Power and Bandwidth Advantage of an H.264 IP Core with 8-16:1 Compressed Reference Frame Store

Power is an increasingly important consideration for the majority of system designers. This is particularly true in the case of small handheld consumer devices such as cameras, camcorders and mobile phones. In such devices, video compression technology is used that relies on power hungry DRAMs to store the reference frames during the encoding and decoding process.