D&R Industry Articles (May 2011)

Featured Article

Software Driven Verification

This paper will discuss the changing landscape of verification caused by the increased importance of software for the success of chip design projects. With software determining an increasing amount of functionality, design teams are adopting virtual prototypes for early software development. Another use case for virtual prototypes is software driven verification, in which testbenches for verification of the hardware are executed in software running on transaction-level models of processors as part of virtual prototypes

Featured Article

Guidelines for SystemC - Debugger Integration

This paper brings-out generic guidelines for debugger integration with SystemC which can be used for other such similar activities. The paper describes how to spawn the SystemC simulation kernel from the debugger context to ensure the control of the simulation by the debugger. The synchronization of debugger control operations like run, step, stop, etc with the SystemC simulation is described. Breakpoint management for the debugger in the SystemC simulation is also described as part of the paper.

Featured Article

Advanced Power Management in Embedded Memory Subsystems

This paper addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SoC designs that contain embedded memory. The paper includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.

Featured Article

Guidelines for Successful SoC Verification in OVM/UVM

With the increasing adoption of OVM/UVM, there is a growing demand for guidelines and best practices to ensure successful SoC verification. This paper will first describe the basic tenets of OVM/UVM, and then it tries to summarize key guidelines to maximize the benefits of using state of the art verification methodology such as OVM/UVM.

Featured Article

TLM 2.0 Standard into Action: Designing Efficient Processor Simulators

This article presents TRAP (Transactional Automatic Processor generator), an innovative ADL targeted to the creation of fast and flexible simulators based on the SystemC language and on the new OSCI Transaction Level Modeling methodology. The modeling of the LEON2 and LEON3 processors is presented to show and assess the features, performance, and capabilities of TRAP.