D&R Industry Articles (August 2011)
Articles for the Week of August 29, 2011
Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP
This paper presents two unique solutions for facilitating functional coverage in VHDL and SystemC. One approach is to use post-simulation Value Change Dump (VCD) files to calculate functional coverage. The other approach, which is applicable only to SystemC, proposes extending the SystemC Verification Library (SCV) to facilitate functional coverage calculation.- Many-Core: Finding the Best Multi-Processing Tile
- Cryptography in software or hardware: It depends on the need
Articles for the Week of August 22, 2011
Ultra Low Jitter Wide Band LC PLL
The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. The PLL is the key to determining high speed link capabilities, since high quality clocks are required to meet bit error rate (BER) specifications of 10-12 to 10-15. An ultra-low jitter wideband LC PLL has been developed to meet the exacting requirements of today's systems.- Hot Chips: the puzzle of many cores
- Transaction Analysis and Debug across Language Boundaries and between Abstraction Levels
- Developing processor-compatible C-code for FPGA hardware acceleration
- Cache-Coherence Verification
Articles for the Week of August 15, 2011
Distributed Video Coding (DVC): Challenges in Implementation and Practical Usage
Distributed Video Coding (DVC) is a new coding paradigm for video compression. This paper highlights gaps and challenges in implementation of DVC and its practical usage.Articles for the Week of August 8, 2011
The Importance of True Randomness in Cryptography
Creating Random Numbers is hard. Especially if all you have available to do it, is digital hardware and deterministic software. Where is the randomness in that? Both are designed to behave predictably, each time, every time. Therefore, hardware and software designers, trying to find unpredictability, have to look outside of their normal operating environment to find it.- How do I reset my FPGA?
- Get control of ARM system cache coherency with ACE verification
- SOCs: IP is the new abstraction
- Minimize leakage power in embedded SoC designs with Multi-Vt cells
Articles for the Week of August 1, 2011
Interconnect Solutions for 40G/100G Systems
One of the key challenges with supporting 40G/100G links is that the SerDes must not only support emerging standards such as XLAUI (40G Ethernet) and CAUI (100G Ethernet) but must continue to support current and legacy interfaces such as 1Gbps Ethernet (SGMII) and 10Gbps Ethernet (XAUI). Multi-protocol support is essential to managing the transition to higher data rates while still supporting legacy standards.- Latches and timing closure: a mixed bag
- An Efficient ASIP Design Methodology
- Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device
- Making your application code multicore ready
- Designing with core-based high-density FPGAs
- Design guidelines for embedded real time face detection application