D&R Industry Articles (January 2012)
Articles for the Week of January 30, 2012
Analog Mixed Signal Verification Methodology (AMSVM)
This paper discusses various disadvantages of methodologies currently in use. Also in this paper there is description of methodology/flow which will help to achieve complete functional verification for Analog Mixed Signal Design/SoC’s. It also provides good confidence about functional verification and correctness of Analog Mixed Signal design.- Programmable logic, SoC simplify power steering, accessory control
- Top 10 Tips for Success with Formal Analysis - Part 2
Articles for the Week of January 23, 2012
DO-254 for Dummies: IP & verification process
Current electronic development is becoming increasingly dependent on predefined IP blocks (more than 35% of elec-tronic components currently in development use IP). It would be very surprising if the aeronautical industry (as well as other safety critical industries) could do without this key element, which is the only solution that can guarantee time to market and sustainability compatible with current requirements.Articles for the Week of January 16, 2012
Improving SystemVerilog UVM Transaction Recording and Modeling
This paper will summarize previous work about SystemVerilog UVM transaction recording, transaction modeling and the supporting transaction recording APIs. This discussion will span a wide spectrum, from simple concepts such as transaction begin and transaction end, to more advanced concepts such as relationships, “tags”, and other transaction attributes.- Leverage Ethernet to improve passenger safety, comfort, and convenience
- Smart Engine for Public Key cryptography
Articles for the Week of January 9, 2012
Additional Articles- AMS and High-speed Interface IP Design Enablement in GLOBALFOUNDRIES 65LPe Process Technology
- How formal MDV can eliminate IP integration uncertainty
- Rethinking embedded memory
Articles for the Week of January 2, 2012
Functional Coverage Analysis for IP Cores and an Approach to Scaledown Overall Simulation Time
This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real challenging task in any digital design development. Consequently, it is necessary to develop new methodologies to improve the quality of functional verification and also to decrease the time for regression convergence.- Shortage of Verification Resources in the Semiconductor industry
- Significance of standardized, interoperable, proven and integration ready stacks for mass adoption of next generation smart surveillance systems