D&R Industry Articles (February 2012)

Featured Article

Mixed-Signal IP Design Challenges in 28 nm and Beyond

This paper presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The paper addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the paper focuses on three main areas where 28-nm technologies pose some unique challenges, Low-Power Design, Restricted Design Rules, and Design for Yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property portfolio.

Featured Article

Application Hardware Modeling: Selective modeling for early prediction of subsystem performances through simulation

The virtual validation of subsystem performances (Pop-up Noise, Signal-to-Noise Ratio, Power supply Noise, Power consumption...) requires the modeling and simulation of complete subsystems. Application Hardware Modeling (AHM) consists in addressing the risks of performance degradation while integrating a Silicon IP in its Integrated Circuit (IC) and this IC on its Printed Circuit Board (PCB). The selection of relevant models for a subsystem performance, along with the creation and validation of models through equivalence checking, are the basics of Application Hardware Modeling for right-on-first-pass subsystems!

Featured Article

Clock Domain Crossing Glitch Detection Using Formal Verification

Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With the integration of multiple designs, various clock domains are introduced. In this paper, we present a solution for finding clock domain crossing glitch using a combination of formal verification and static timing analysis techniques. This paper also talks about leveraging a formal verification tool to do sequential equivalence checking between a buggy design and bug fixed design if CDC glitch is found in late design stages

Featured Article

Refactoring Hardware Algorithms to Functional Timed SystemC Models

SystemC Modelling is an emerging technology used for SoC Verification and termed as Virtual Platforms. This paper presents a systematic approach of converting a hardware algorithm into a functional timed SystemC model and simulation speed improvement techniques that could be incorporated.