D&R Industry Articles (May 2012)

Featured Article

Analog IP Nirvana: a modular based design methodology for addressing the agility

In this paper we propose a modular design methodology which can handle the agility of analog IP and help to achieve the first pass silicon. A case on PLL design will be discussed to highlight the key benefit of this design methodology.

Featured Article

AMBA 4 ACE for Heterogeneous Multiprocessing SoCs

AMBA 4 ACE adds system-level coherency support to the AMBA 4 specifications. By enabling cache coherency between the high- performance ARM Cortex-A15 MPCore processor and software-compatible high- efficiency Cortex-A7 MPCore processor it enables energy savings through heterogeneous multiprocessing, termed ‘big.LITTLE’ by ARM.

Featured Article

3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology

In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.

Featured Article

Channel Core Flex: An Advanced Channeliser for Next Generation Digital Radio Receivers

This paper discusses the relative merits of the various digital signal processing techniques used to channelise signals. ChannelCore Flex (CCF) exploits all of these strengths to provide a flexible channeliser architecture that is capable of supporting thousands of independently defined channels in a single FPGA. The CCF core can be tailored at build-time to support the user’s generic channel plan and required level of flexibility. The precise channel plan can then be loaded and updated at run-time. The FPGA resources required to implement CCF in a Xilinx Spartan-6 LX100 are presented for an example channel plan with 1024 channels of various bandwidths.