D&R Industry Articles (September 2012)

Featured Article

Designing a reset-aware OVM testbench

This paper describes how to design your testbench to make it reset-aware, starting by discussing how this affects the testbench architecture, and then going into more details about each verification component and what changes are required for it to take into consideration the reset conditions.

Featured Article

Validating Software in Commercial Smart Transmitter for Safety-Critical Applications

Industries, including nuclear industries, depend on the transmitters (for monitoring process parameters) that are available in the market from reputed manufacturers. This work aims at answering the question of how to validate and qualify a smart transmitter, containing pre-developed software (PDS) in it, for its suitability in safety-critical application when there is no access to the software development process documentation.

Featured Article

SystemC library supporting OVM compliant verification methodology

This paper describes the SystemC library that support Open Verification Methodology as defined by Mentor Graphics and Cadence with their SystemVerilog–based approach. Application of the library in development of a testbench for the simple component is presented. Advantages of its other possible uses are pointed to.

Featured Article

Physical Attacks against Cryptographic Implementations

Since the advent of side channel attacks, classical cryptanalysis is no longer sufficient to ensure the security of cryptographic algorithms. In practice, the implementation of algorithms on electronic devices is a potential source of leakage that an attacker can use to completely break a system. The injection of faults during the execution of cryptographic algorithm is considered as an intrusive side channel method because secret information may leak from malicious modifications of the device's behavior.