D&R Industry Articles (January 2013)
Articles for the Week of January 28, 2013
Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol
This paper describes how a reference verification platform built with the Discovery VIP for the AMBA ACE protocol can be utilized to accelerate the verification of multi-core SoCs. Also highlighted are Synopsys verification technologies like Discovery Visualization Environment (DVE) and Protocol Analyzer for advanced debug of the AMBA 4 AXI/ACE protocols.- 10 software tips for hardware engineers
- Addressing signal electromigration (EM) in today’s complex digital designs
- Verification IP: the questions you should ask
- Developing FPGA applications for Edition 2 of the IEC 61508 Safety Standard
Articles for the Week of January 21, 2013
An ESD efficient, Generic Low Power Wake up methodology in an SOC
As the semiconductor industry is moving towards lower technology nodes, more and more complexity is being introduced in the design to beat the competition and provide most innovative solution to cater the needs. One of the biggest challenges that the designer faces is in terms of the keeping the power budgets of the chip within the specification and even innovate to reduce the current numbers. Depending on the application requirements, the designers have to tune up the power profile of the SoC. There are various ways to do so like dynamically changing frequency and voltage of operation, considering system level contributions to power consumption, using various modes of operation etc. In most of the cases, SoC has to support various power modes like Run mode, Sleep mode, Halt mode etc. Different power numbers are defined for each mode. Run modes can further be divided in various sub modes depending on application.- Reap the benefits of a general-purpose interface USB 3.0 device controller
- Overcoming the embedded CPU performance wall
- Tackling large-scale SoC and FPGA prototyping debug challenges
- Using SoCs for portable medical equipment
Articles for the Week of January 14, 2013
An Example Verification Environment for Different Types of Processor Models
This study describes a C code wrapper that supports ARM DSM functional verification and a TLM based verification with a unified test code on ARM CortexM3 processor.- Circuit reliability challenges for the automotive industry
- Integrating large-capacity memory in advanced-node SoCs
- Optimizing efficiency and flexibility in DSP systems
Articles for the Week of January 7, 2013
The Case for Developing Custom Analog
Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.Articles for the Week of December 31, 2012
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