D&R Industry Articles (February 2013)

Featured Article

State of RTL based design - is it time to move beyond?

This paper looks at the history of logic synthesis technology and its impact on design productivity and design reuse. It then goes on to discuss a few technologies that have the potential to boost design productivity in a similar manner to the way logic synthesis has over the last 25 years. It suggests Core-Based Design methodology as a potential solution and identifies areas that need further work.

Featured Article

Silicon-Accurate Fractional-N PLL Design

Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief description of the key performance parameter – jitter.

Featured Article

General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA

Today's FPGAs have the capability to contain a complex and large system-level design. However, in some cases, there is a requirement for these designs to be partitioned among several FPGAs for validation or prototyping. But, splitting the design into several FPGAs can create various partitioning issues, especially for relatively large designs with complex connectivity. These issues could possibly be circumvented if certain guidelines are followed. This paper talks about the general partitioning challenges and the guidelines that can be followed to get past these issues

Featured Article

Using 3rd Party IP in ASIC/SoC Design

3rd Party IP has become a buzz word since the Semiconductor industry has shifted gears to Fab-lite and eventually to Design-lite models in last few years. The new business models have opened the doors in many companies to overcome some of the internal weakness about possessing any IPs/design competencies to do a next generation ASIC/SoC designs. There have been multiple debates about which and to what extent should a company look into 3rd party IP. This paper outlines some best practices for using the ecosystem as well as some of the common challenges in integrating and using 3rd Party IPs in today’s high-end ASIC/SoCs.