D&R Industry Articles (April 2013)

Featured Article

The Power of Developing Hardware and Software in Parallel

As the mobile development cycles keep shrinking, innovative companies are using a number of strategies to balance complexity of software development with aggressive schedules. Starting software development early and getting to market early is one of the strategies that innovative mobile software developers are using to beat the clock. By following a phased development process, sharing early work with customers and their ecosystem partners, mobile devices are reaching market earlier and with innovative features.

Featured Article

A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A

This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP(Quadratic Polynomial Permutation) interleaver of 3GPP LTE/LTE-A standards.

Featured Article

System Test using JTAG

Though the JTAG IEEE 1149.1 standard is widely used for board level test, this paper would show the applications of the same standard at the system level test. The system level test using JTAG techniques can be very helpful to support and maintenance personnel long after a system has been assembled in a manufacturing environment and installed at a customer location.

Featured Article

A First time right design methodology for successful development of automotive SoC products

This paper describes the methodology employed during the development of a System on Chip (SoC) platform developed for automotive applications. The methodology is based on the following major aspects: requirement driven development approach based on reusable IP core as the base for SoC integration and development; functional coverage based verification approach providing 100% coverage to requirements; FMEA based risk identification and tracking approach.

Featured Article

Building Your UVM Verification Environment for Cache Coherent Interconnects

This paper will focus on building a Universal Verification Methodology (UVM) based verification environment that will help you verify an ACE-based interconnect. We will use ARM CoreLink™ CCI-400 as the design under test (DUT) in order to demonstrate all the necessary steps that are required to confidently sign off that your design was verified.