D&R Industry Articles (May 2013)

Featured Article

Managing Requirements Tracking, Implementation and Sign-off for Embedded Systems

This document describes the issues faced when building hardware and software systems where the success of the project is dependant on requirements being fully supported and tested. Where the cost of failure is high there is a greater necessity for a robust requirements sign‐off capability. This particularly applies to systems where the financial cost of recalling a failing product is prohibitive and/or there is a high safety factor which is typical of embedded systems.

Featured Article

Generic DDR Behavioural Model

This paper represents a generic executable architecture. It represents the efficient behaviour of the Memory Model to be used for verification of SOC communicating with DDR SDRAMs or can be used as the third party Model verification (passive element). Paper shows the capability as standalone VIP architecture and also represents the market value of DDR model in the present technical era with different technical views and challenges faced. It also givessolution of supporting different part number of established DDR vendors like Micron, Elpida, Samsung etc.

Featured Article

Automated ECO Flow for overall cycle time reduction

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity. The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turnaround time.

Featured Article

SoC Interconnect Verification Challenge

This paper describes the author’s experiences in verifying multi-protocol SoC interconnects, it explains the pitfalls of such verification and describes a solution to allow easy reconfiguration of a generic verification environment. We show how issues have been resolved and propose a generic approach for SoC interconnect verification.