D&R Industry Articles (January 2014)

Featured Article

A design methodology using Power-Grid Prototyping to optimize Area Performance of SoCs

This paper first describes a methodology for power grid optimization leveraging early static IR flow and correlating with existing sign-off results. It also presents a methodology for doing early dynamic IR drop analysis, which can identify potential overdesigns in the grid to save valuable signal routing area. It outlines the impact of Metal6 power grid width variations on Static and dynamic IR drop using STB SoC in 40 nm Wire bond chip.

Featured Article

Using Transactions to Effectively Debug Large SoC Designs

SoC designs are large designs made by combining other large designs. A typical SoC has many communication pathways and a large amount of parallel activity. In order to debug these kinds of designs effectively new approaches must be taken. This paper discusses the requirements for effective debug in the face of today's large SoCs, outlining real world example and making some recommendations for easier solutions. This includes transaction based debug, with special attribute recording. These special attributes help identify "connected" transactions.

Featured Article

Moving PCI Express to Mobile (M-PCIe)

This paper will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the paper will detail those issues. A basic understanding of PCI Express concepts is helpful but not required.