D&R Industry Articles (March 2014)

Featured Article

Plug-n-play UVM Environment for Verification of Interrupts in an IP

This paper proposes a method to mimic the actual behavior of the embedded processor for interrupt handling in standalone IP verification environment. Use of UVM components done to make a reusable, parameterizable and real time interrupt handler for UVM testbench. The method proposed in this paper describes an automated interrupt handler logic which runs parallel to entire environment.

Featured Article

Reusable Test-Case Methodology for SoC Verification

This paper proposes a novel Test-Case methodology for System on chip (SoC) Verification in order to achieve high levels of reusability. It surveys the challenges of a traditional SoC Test-Case Methodology and then proposes a solution.

Featured Article

Using IP-XACT Metadata for a TLM Modeling Flow

A metadata driven methodology allows automatic generation of netlists and design IP skeletons from a central database that contains registers, ports, interfaces, and other common design data. IP-XACT is commonly used to store the metadata. This paper explores how to use IP-XACT to represent the necessary data to generate SystemC/TLM netlists and components

Featured Article

Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs

This paper describes an efficient, forward-looking architecture that enables handling of various form factors of LTE base stations with minimal software modification and without architecture changes. The architecture proposed allows easy migration to the next generation SoCs as well as to more powerful SoCs of the same generation. Our implementation of this architecture has now migrated two generations of SoCs for LTE Release 9 small and macro cells, and is ready for migration to a multi-sector, LTE-A macro base station.

Featured Article

Scalable Architectures for Analog IP on Advanced Process Nodes

This paper elaborates on how ADCs can work with Moore's Law to move with the power and area scaling trends that are common for digital circuits. It will compare the main ADC architectures and conclude that the Successive-Approximation Register (SAR) based ADC is very well positioned as the architecture of choice for medium- and high-speed ADCs in modern SoCs, especially in 28-nm processes and beyond. It will describe implementations of the SAR ADC architecture that reduce power consumption and area usage dramatically, enabling SoC designers to successfully integrate these analog components in their next SoCs.