D&R Industry Articles (May 2014)

Featured Article

CPF Based Verification of an SoC - Lessons Learnt

Power Management keeps being a very valuable asset for mobile applications. CPF (Common Power Format) is a common file format to describe the power structure of the design in the early design stages that makes it a very critical design step input of the VLSI design flow. It is possible to verify a design from low power point of view using lint tools and/or simulations without CPF, but not as effective as a CPF based simulation methodology.

Featured Article

Design Rights Management of Intellectual Property (IP) Cores in SoPC designs

This paper presents a Design Rights Management methodology used in a practical EDA tool suite: IP-Idol, developed by the start-up Algodone, based in Montpellier-France. It consists to encrypt and decrypt Hardware Description Language models (following IEEE 1735 and part of IEEE 1800 standards) of some Intellectual Property Cores (IP) in SoPC (System on Programmable Chip) with a strategy model where Algodone plays the role of a trusted third party.

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Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs

Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.

Featured Article

Auto Clock Generation in a SoC

This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file. The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.