D&R Industry Articles (June 2014)

Featured Article

Skillfully Emulating a System on Chip

Time to market is most important criteria for survival in the IC design industry. For this one should produce low cost good quality silicon in lesser time. In order to achieve this, design should be validated well before tape out in application area ecosystem and all software should be ready before silicon comes in the lab. This objective can be achieved by porting design and test environment to the emulator. This paper deals with art of skillfully porting a SoC on to emulator, architecting virtual evaluation board (EVB) and benefits of using emulation.

Featured Article

Guide to Choosing the Best LDO for Your Application

LDOs are so common inside portable devices, state of the art power management integrated circuits (PMICs) for smartphones and other portable devices include over a dozen LDOs. To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With so many different LDO applications and the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a comprehensive list of all of the different LDO parameters with definitions, the most common applications of LDOs, and which parameters are critical for each.

Featured Article

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, quality and maintainability of the translated code. VHDL and SystemC are frequently co-simulated by architects as well as verification teams. This paper explores optimization scenarios that affect the cosimulation performance, resulting in 30% faster co-simulation. In addition to the plain VHDL-to-SystemC conversion, there are possibilities of alternate implementations for a SystemC model. This paper explores these alternate scenarios to get 25% better simulation-speed. The optimization methodologies in this paper are relevant to architects, designers, verification-teams, IP design-houses that need to provide high-speed simulation-models, and can be used for optimizing cosimulation tools as well system-level models.

Featured Article

Conquering the challenges of PCIe with NVMe in order to deliver highly competitive Enterprise PCIe SSD

To help leading storage companies address the booming demand of PCI SSD (Solid State Drive), PLDA enhances the end-to-end data integrity functionality of its PCIe soft IP products and showcases a NVMe demo on its hardware.

Featured Article

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.