D&R Industry Articles (August 2014)

Featured Article

Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP

With the declining gate length in new process technologies, static power dissipation becomes a bigger problem. Nowadays, power is replacing performance as the key competitive metrics in SoC. This triggers the need for multi-voltage management techniques.CPF or Common Power Format provides techniques and concepts that can be applied at various stages throughout low-power SoC design development to express the power intent of an IC design.

Featured Article

Intelligent Vt structuring to avoid Temperature Inversion for Performance gain

In the modern era, there is a requirement of achieving high frequency targets with lower power consumption. Achieving both the targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects like Temperature Inversion comes into picture.

Featured Article

GC Nano - User Interface (UI) Acceleration

Crisp, clear, and responsive user interface HMI (human machine interface) has become equally important to the user experience as the content or the device form factor. A beautifully crafted smartphone that uses a combination of brushed titanium and smudge-proof glass may look great in the hand, but the user will quickly opt for another product if the user interface stutters or the screen is hard to read because of aliased and inconsistent fonts. The same scenario also applies to HMI in wearables and IoT devices, which is the focus of this white paper.

Featured Article

The silicon enigma: Bridging the gap between simulation and silicon

VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.