D&R Industry Articles (September 2014)

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RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor

Development of miniature high performance data processing systems needs combined optimization of algorithms and processor architecture. Today's microelectronics allows designing almost all the computer architectures as SoC. The paper is devoted to the practical realization of SINS algorithms by means of SoC.

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Reducing Power Consumption while increasing SoC Performance

Designers of today's high-performance multi-client SoCs struggle to achieve the best possible performance/watt for their designs. Every generation of product must improve the customer's user experience by delivering more performance. While at the same time battery life must increase with each subsequent product generation.

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An innovative methodology to reduce routing capacitance of ADC channels

As the technology nodes are shrinking, achieving performance metrics for analog circuits are becoming more challenging. Moreover RLC parasitic and noise effects have hampered the performance of circuits on SoC, especially for the sensitive analog circuits like ADCs, Oscillators etc. With more and more complex designs with frequencies in Ghz range, noise sources have increased considerably which affects the intended behavior of the signal.

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A Realtime 1080P30 H.264 Encoder System on a Zynq Device

The Zynq all programmable System On a Chip is a recently introduced device from Xilinx which incorporates two ARM A9 CPU cores, I/O peripherals, memory controller, and programmable logic. This paper describes the implementation of a 1080P30 realtime H.264 encoder system on the device.