D&R Industry Articles (June 2015)
Articles for the Week of June 29, 2015
Ethernet as IP: The Time Has Come
In this paper, we will look at the economics of integrating the Ethernet Physical Layer, and what options exist for product managers and engineers seeking to shrink their power and area footprints, while achieving cost reductionArticles for the Week of June 22, 2015
Ten reasons interconnect matters
Interconnect is the Rodney Dangerfield of IP blocks. It gets no respect. It connects hundreds of disparate IP blocks, each with hundreds of interface signals, and dozens of transaction protocol attributes. It does it in a way that each IP need not know the protocol details of any other. It also provides for the data access requirements of each IP, and does it physically distributed across the chip floorplan. Interconnect fabric technology is sophisticated, and very important for modern chip designs. Following are ten reasons why interconnect matters.- Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs
- Achieving Better Productivity with Faster Synthesis
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Sequential architecture for absolutely NO hold requirement in the Shift path
Articles for the Week of June 15, 2015
Delay Characterization for Sequential Cell
This paper discusses the models and methodology that are used commonly for characterizing the timing parameters of various sequential logic cells which are key elements of synchronous design.Articles for the Week of June 8, 2015
Ensuring Security in the Connected Home
Security plays a critical role in the market adoption of the IoT. It's easy to imagine a scenario in which an intruder uses a connected appliance to gain control of someone's smart home or access to their personal information.- Sorting Out Embedded Vision Systems
- Documentation First! unifies design flow
- Physical Lint -- Better RTL Quality Improves Design Convergence
- An efficient way of loading data packets and checking data integrity of memories in SoC verification environment
Articles for the Week of June 1, 2015
Additional Articles- SoC RTL Signoff: Divide & Conquer with Abstract Models
- Structural netlist efficiently verifies analog IP
- 10 Tips for designing a Hardware Abstraction Layer (HAL)
- Platforms Open Door to New Factory Automation Era
- Robust Low power Architecture verification Strategy
- High Density - Low power Flip-Flop
- Extraction Challenges Grow in Advanced Nanometer IC Design