D&R Industry Articles (January 2016)
Articles for the Week of January 25, 2016
Reusable MAC Design for Various Wireless Connectivity Protocols
This paper presents how the 8-bit customized micro-processor could implement the MAC operation that sufficiently co-processes with main CPU as well as meets the timing requirement for controlling various PHY and RF. Because IEEE 802.11ac VHT MAC is the most challengeable protocol to be designed by SW among the introduced connectivity technologies, we evaluated our MAC design with VHT MAC protocol and generated several constraints, which are not critical points to our programmable and common platform concepts.Articles for the Week of January 18, 2016
True Random Number Generators for Truly Secure Systems
Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy.- How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity
- System Security: A Model from Medieval History
- NoC Interconnect Fabric IP Improves SoC Power, Performance and Area
Articles for the Week of January 11, 2016
Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim
In this paper we present a methodology to model and verify a mixed-signal IP using SystemVerilog in Virtuoso and NCsim. We take our 12.5Gbps transmitter (TX) design as an example to explain the method we propose. This TX is designed to operate at programmable data rates from 1.25Gbps – 12.5Gbps and to support requirements of multiple serial protocols like USB, PCIe, and SATA. Interaction between AFE and Digital is key towards proper implementation of features like Feed Forward Equalization (FFE), programmable output swing and power management states.Articles for the Week of January 4, 2016
Solutions to Resolve Traditional PHY Verification Challenges
This article describes the challenges faced with the traditional approach for the PHY verification. During this article, while going into details of PHY verification, we will discuss the solution provided to do the PHY verification with minimal effort, without investing in understanding of the multiple protocol stacks being used by PHY’s.- Enable IoT ASIC Design Using Platforms
- When System Designers Must Care About Silicon IP
- Hold Fixing Techniques