D&R Industry Articles (February 2017)

Featured Article

Design Rule Checks (DRC) - A Practical View for 28nm Technology

The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards.

Featured Article

Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff

As SoC increases in complexity, one of the elements that are becoming critical is effective power estimation and correlation with silicon. Early and accurate SoC power estimation is becoming a challenge. Using traditional flow, an accurate power assessment cannot be guaranteed until gate level netlist after timing closure is available. This can lead to late design changes. The issue is exacerbated if the power measurements do not correlate well with silicon leading to costly design re-spins.

Featured Article

Hybrid Hardware Architecture for Low Complexity Motion Estimation Algorithm

Nowadays hybrid hardware architecture (HHA) becomes increasingly popular in embedded systems (ES). In this paper HHA is presented for low bit depth motion estimation (ME) algorithm. Intellectual property (IP) core is designed for ME algorithm by using field programmable gate array (FPGA) and this IP is integrated with processor system (PS) to investigate its performance in an ES. Designed ME based IP has data bus of size 32bits and is working properly up to 200 MHz. Experiments show that the HHA is integrated successfully and gives expected results in real time.

Featured Article

Configurable Microprocessor for Life Essential Devices

This paper will explore how processors have evolved with attributes such as configurability and extensibility to enable the next generation of electronics.