D&R Industry Articles (August 2017)

Featured Article

The case for integrating FPGA fabrics with CPU architectures

Physics restricts how much further process geometry shrinkage can take us in terms of boosting processor throughput.

Featured Article

Addressing Clock Tree Synthesis Challenges

Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.

Featured Article

UVM Sequence Library - Usage, Advantages, and Limitations

Increasing size and complexity of designs and systems have made it mandatory to randomize the stimulus driven to these designs, as directed scenarios will take more time to complete the verification. Along with randomization, there is a need of same design code to be exercised multiple times, this is achieved through multiple simulations of same test sequence. The test sequence will include the feature specific randomization. During multiple runs of test sequence, the randomization will provide different stimulus for design.