D&R Industry Articles (October 2017)

Featured Article

The Battle of Data center Interconnect Fabric

With the exponential increase in off-chip bandwidth requirement, chip-to-chip interconnect is turning out to be the bottleneck of the information highway. Such bottlenecks invariably drive a new wave of innovation. During 1990s and around the turn of the millennium, rapid adoption of personal computers and development of various IO devices fuelled early innovations in interconnect technology and interfaces such as SATA, SAS, USB, PCIe were defined.

Featured Article

Platform Software Verification Framework Solution for Safety Critical Systems

Here, in this paper, we shall discuss the challenges involved in various verification platform software framework solutions for ARINC-653-based operating system and how a single framework, PSW eIHTestCon can resolve these challenges.

Featured Article

Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)

SoC (System-on-Chip) Verification effort mainly includes three key phases: Planning, Development and Verification. Planning phase includes preparing verification strategy in terms of Test plan, Coverage plan and Assertion plan. Verification of complex SoC requires all micro level data (i.e. Individual Test status in Regression, Functional and Code Coverage numbers, etc.) to be collected at a common place for better tracking.